/*
* Do not change Module name
*/
module main(..);
endmodule
module rateDivider(select, clk, reset, par_load, enable, q);
input [1:0] select;
input clk;
input reset;
input par_load;
input enable;
input q;
reg [27:0] d;
// select rate
always @(*)
begin
if (select == 2'b00)
d <= 0;
else if (select == 2'b01)
d <= 49,999,999;
else if (select == 2'b10)
d <= 99,999,999;
else if (select == 2'b11)
d <= 199,999,999;
else
d <= 0;
end
// instantiate rateCounter here, feed mux into it
rateCounter my_rateCounter (
.d(d),
.clk(clk),
.reset(reset),
.par_load(par_load),
.enable(enable)
.q(q)
)
endmodule
module rateCounter(d, clk, reset, par_load, enable, q);
input [27:0] d;
input clk;
// determine need
input reset;
input par_load;
input enable;
output q;
output EN_out
reg q;
always @(posedge clk)
begin
if (reset == 1'b0)
q <= 0;
else if (par_load == 1'b1)
q <= d;
else if (enable == 1'b1)
begin
if (q == 0) // check use of decimal here won't cause issue
q <= d;
else
q <= q - 1'b1;
end
assign EN_out = (q == 0) ? 1 : 0;
endmodule
module DisplayCounter(..);
//
always @(posedge clk)
begin
end
endmodule;
module tflip(t, reset_n, clk, q);
//width 1
input t;
input reset_n;
input clk;
output q;
reg q;
always @(posedge clk, negedge reset_n)
begin
if (~ reset_n)
q <= 0;
else
q <= t ^ q;
end
endmodule
module mux2to1(x, y, s, m);
input x; //selected when s is 0
input y; //selected when s is 1
input s; //select signal
output m; //output
assign m = s & y | ~s & x;
// OR
// assign m = s ? y : x;
endmodule
module mux4to1(u, v, w, x, s0, s1, m);
input u; //selected when s1s0 is 00
input v; //selected when s1s0 is 01
input w; //selected when s1s0 is 10
input x; //selected when s1s0 is 11
input s0; //first bit of select signal
input s1; //second bit of select signal
output m; //output
wire wire1;
wire wire2;
mux2to1 u0(
.x(u),
.y(v),
.s(s0),
.m(wire1)
);
mux2to1 u1(
.x(w),
.y(x),
.s(s0),
.m(wire2)
);
mux2to1 u2(
.x(wire1),
.y(wire2),
.s(s1),
.m(m)
);
endmodule
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