module sum(a,b,carrycero,result);
// se declaran las entradas
input [3:0] a; //primer numero de 4 bits que se va a sumar
input [3:0] b;//segundo numero de 4 bits que se va a sumar
input carrycero;//el carry inicial
output [4:0] result;//resultado de 5 bits
wire [3:0] g,p;//variables de sumador manchester
wire [3:0] carry;//carry para los 4 bits
//se asigna cada bit de ambos números a las variables del sumador
assign g[0] = a[0] & b[0];
assign p[0] = a[0] ^ b[0];
assign g[1] = a[1] & b[1];
assign p[1] = a[1] ^ b[1];
assign g[2] = a[2] & b[2];
assign p[2] = a[2] ^ b[2];
assign g[3] = a[3] & b[3];
assign p[3] = a[3] ^ b[3];
//se efectua la ecuación del sumador manchester para cada carry
// C[i+1] = g[i] + p[i]*c[i]
// C[0] = g[0] + p[0]*carrycero
assign carry[0] = g[0] | (p[0] & carrycero);
assign carry[1] = g[1] | p[1] & (g[0] | (p[0] & carrycero));
assign carry[2] = g[2] | p[2] & (g[1]|p[1] & (g[0] | (p[0] &carrycero)));
assign carry[3] = g[3] | p[3] & (g[2]|p[2] & (g[1] | (p[1] & g[0] | (p[0] &carrycero))));
//se realiza la suma para cada bit y se asigna a cada bit de result
assign result [0]=a[0]^b[0]^carrycero; // a(bit 0) XOR b(bit 0) XOR carrycero(el carry inicial)
assign result [1]=a[1]^b[1]^carry[0]; // a(bit 1) XOR b(bit 1) XOR carry(bit 0)
assign result [2]=a[2]^b[2]^carry[1]; // a(bit 2) XOR b(bit 2) XOR carry(bit 1)
assign result [3]=a[3]^b[3]^carry[2]; // a(bit 3) XOR b(bit 3) XOR carry(bit 2)
assign result [4]= carry[3]; // se le asigna el valor del bit 3 del carry al bit 4 del resultado
// se realiza la suma bit con bit mas el carry generado por la suma del bit anterior, ya que las ecuaciones de manchester nos calculan el carry que se va a sumar en el siguiente estado
endmodule
// se finaliza la suma y ahora se aplica un testbench
module stimulus;
// Inputs
// se agregan como entrada los registros a y b que son los números de 4 bits a los que se les asignaran valores para realizar la simulación
reg [3:0] a;
reg [3:0] b;
reg carrycero;// se agrega como entrada el registro carrycero que sera el carry inicial de la suma
// Outputs
wire [4:0] result; // resultado de 5 bits que contemplan una suma máxima de 1111(4 bits) + 1111(4 bits) = 11110(5bits)
// Instantiate the Unit Under Test (UUT)
//se relacionan las variables del modulo sum con las del testbench (modulo stimulus)
//con la siguiente notación: .v0(v1)
//v0 = variable del modulo sum
//v1 = variable del testbench
sum uut (
.a(a),
.b(b),
.carrycero(carrycero),
.result(result)
);
initial begin
// se inicializan las entradas, con valor 0
a = 0;
b = 0;
carrycero= 0; //se asigna por defecto 0 ya que para el primer bit de una suma no hay carry de entrada
// se realizan delays de 20ns y se asigan valores de 4 bits a a y b
#20 a = 4'b0001;
b= 4'b0001;
#20 a = 4'b0011;
b= 4'b0011;
#20 a = 4'b0111;
b= 4'b0111;
#20 a = 4'b1111;
b= 4'b1111;
#20 a = 4'b0101;
b= 4'b0101;
#20 a = 4'b1001;
b= 4'b0110;
#20 a = 4'b0101;
b= 4'b1111;
end
//se imprime la suma mostrando los sumandos y el resultado
initial begin
$monitor(" %b\n + %b\n = %b \n",a,b,result); //se imprime primero a en binario y se salta renglon, luego imprime el simbolo de suma, b en binario y salta renglon, y finalmente se imprime el simbolo de igual y result en binario
end
endmodule
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