/*
* Do not change Module name
*/
module main (u1, u2, clock);
input u1;
input u2;
input clock;
wire dnup;
wire carry;
wire borrow;
wire divi;
ADPLL PD(u2, u1, dnup);
ADPLL_LF lp(clock, dnup, carry, borrow);
DCO dc1(clock, carry, borrow,divi);
Divider div(divi, u2);
endmodule
module ADPLL(u1, u2, Q);
input u1;
input u2;
output Q;
assign Q = (u1^u2);
endmodule
module ADPLL_LF(kclk, dnup, carry, borrow);
input kclk;
input dnup;
output borrow;
output carry;
reg carry;
reg borrow;
reg [7:0] up;
reg [7:0] dn;
reg [7:0] K;
initial
begin
K = 8'b00010000;
dn = 1'b0;
up = 1'b0;
end
always@ (posedge kclk)
begin
if(dnup == 1)
begin
dn = (dn + 1'b1) % K;
end
else if(dnup == 0)
begin
up = (up + 1'b1) % K;
end
end
always@ (up)
begin
if(up >= (K>>1))
begin
carry = 1'b1;
end
else if(up < (K>>1))
begin
carry = 1'b0;
end
end
always@ (dn)
begin
if(dn >= (K>>1))
begin
borrow = 1'b1;
end
else if(dn < (K>>1))
begin
borrow = 1'b0;
end
end
endmodule
module DCO (IDclk, carry, borrow, u12);
input IDclk;
input carry;
input borrow;
output u12;
wire IDout;
reg toggleFF;
reg carryL;
reg carryH;
reg borrowL;
reg borrowH;
initial
begin
toggleFF = 1'b0;
carryL = 1'b0;
carryH = 1'b0;
borrowL = 1'b0;
borrowH = 1'b0;
end
always@ (posedge IDclk)
begin
if(carryH == 1'b1 && toggleFF == 1'b0)
begin
carryH = 1'b0;
end
else if(carryL == 1'b1 && toggleFF == 1'b0)
begin
carryL = 1'b0;
carryH = 1'b1;
toggleFF = !toggleFF;
end
else if (borrowL == 1'b1 && toggleFF == 1'b1)
begin
borrowL = 1'b0;
end
else if (borrowH == 1'b1 && toggleFF == 1'b1)
begin
borrowH = 1'b0;
borrowL = 1'b1;
toggleFF = !toggleFF;
end
else
toggleFF = !toggleFF;
end
always@ (posedge carry)
begin
if(toggleFF == 1'b0)
carryL = 1'b1;
else if (toggleFF == 1'b1)
carryH = 1'b1;
end
always@ (posedge borrow)
begin
if(toggleFF == 1'b0)
borrowL = 1'b1;
else if (toggleFF == 1'b1)
borrowH = 1'b1;
end
assign IDout = (!IDclk)&(!toggleFF);
assign u12 = IDout;
endmodule
module Divider (clk , out_clk );
output out_clk ;
input clk ;
reg [1:0]m;
initial
m = 0;
always @ (posedge clk)
begin
m <= m + 1;
end
assign out_clk = m[1];
endmodule
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